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1 ? fn8179.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copy right intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x9315 low noise, low power, 32 taps digitally controlled potentiometer (xdcp?) the intersil x9315 is a digitally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a 3-wire interface. the potentiometer is implemen ted by a resistor array composed of 31 resistive elements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the cs , u/d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a th ree-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: ? control ? parameter adjustments ? signal processing features ? solid-state potentiometer ? 3-wire serial interface ? 32 wiper tap points - wiper position stored in nonvolatile memory and recalled on power-up ? 31 resistive elements - temperature compensated - end to end resistance range 20% - terminal voltage, 0 to v cc ? low power cmos -v cc = 2.7v or 5v - active current, 50/400a max. - standby current, 1a max. ? high reliability - endurance, 100,000 data changes per bit - register data retention, 100 years ?r total values = 10k ? , 50k ? , 100k ? ? packages - 8 ld soic, msop and pdip ? pb-free plus anneal available (rohs compliant) block diagram 5-bit up/down counter 5-bit nonvolatile memory store and recall control circuitry one of decoder resistor array r h /v h u/d inc cs transfer gates thirty v cc v ss r l /v l r w /v w control and memory up/down (u/d ) increment (inc ) device select (cs ) v cc (supply voltage) v ss (ground) r h /v h r w /v w r l /v l general detailed 0 1 2 28 29 30 31 two data sheet september 15, 2005
2 fn8179.1 september 15, 2005 ordering information part number part marking v cc limits (v) r total (k ? ) temp range (c) package x9315wm* aaw 5 10% 10 0 to 70 8 ld msop x9315wmz* (note) ddt 0 to 70 8 ld msop (pb-free) x9315wmi* aax -40 to 85 8 ld msop x9315wmiz* (note) akw -40 to 85 8 ld msop (pb-free) x9315wp x9315wp 0 to 70 8 ld pdip x9315wpi x9315wp i -40 to 85 8 ld pdip x9315ws* x9315w 0 to 70 8 ld soic x9315wsz* (note) x9315w z 0 to 70 8 ld soic (pb-free) x9315wsi* x9315w i -40 to 85 8 ld soic x9315wsiz* (note) x9315w z i -40 to 85 8 ld soic (pb-free) x9315um* 50 0 to 70 8 ld msop x9315umz* (note) dds 0 to 70 8 ld msop (pb-free) x9315umi* aeb -40 to 85 8 ld msop x9315umiz* (note) ddr -40 to 85 8 ld msop (pb-free) x9315up x9315up 0 to 70 8 ld pdip x9315upi x9315up i -40 to 85 8 ld pdip x9315us* x9315u 0 to 70 8 ld soic x9315usz* (note) x9315u z 0 to 70 8 ld soic (pb-free) x9315usi* x9315u i -40 to 85 8 ld soic x9315usiz* (note) x9315u z i -40 to 85 8 ld soic (pb-free) x9315tm* aej 100 0 to 70 8 ld msop x9315tmz* (note) ddn 0 to 70 8 ld msop (pb-free) x9315tmi* adz -40 to 85 8 ld msop x9315tmiz* (note) ddl -40 to 85 8 ld msop (pb-free) x9315tp x9315tp 0 to 70 8 ld pdip x9315tpi x9315tp i -40 to 85 8 ld pdip x9315ts* x9315t 0 to 70 8 ld soic x9315tsz* (note) x9315t z 0 to 70 8 ld soic (pb-free) x9315tsi* x9315t i -40 to 85 8 ld soic x9315tsiz* (note) x9315t z i -40 to 85 8 ld soic (pb-free) x9315
3 fn8179.1 september 15, 2005 x9315tp-2.7 x9315tp f 2.7-5.5 10 0 to 70 8 ld pdip x9315tpi-2.7 x9315tp g -40 to 85 8 ld pdip x9315wm-2.7* aau 0 to 70 8 ld msop x9315wmz-2.7* (note) aoi 0 to 70 8 ld msop (pb-free) x9315wmi-2.7* aav -40 to 85 8 ld msop x9315wmiz-2.7* (note) -40 to 85 8 ld msop (pb-free) x9315wp-2.7 x9315wp f 0 to 70 8 ld pdip x9315wpi-2.7 x9315wp g -40 to 85 8 ld pdip x9315ws-2.7* x9315w f 0 to 70 8 ld soic x9315wsz-2.7* (note) x9315w z f 0 to 70 8 ld soic (pb-free) x9315wsi-2.7* x9315w g -40 to 85 8 ld soic x9315wsiz-2.7* (note) x9315w z g -40 to 85 8 ld soic (pb-free) x9315um-2.7* aek 50 0 to 70 8 ld msop x9315umz-2.7* (note) aku 0 to 70 8 ld msop (pb-free) x9315umi-2.7* aea -40 to 85 8 ld msop x9315umiz-2.7* (note) ajg -40 to 85 8 ld msop (pb-free) x9315up-2.7 0 to 70 8 ld pdip x9315upi-2.7 -40 to 85 8 ld pdip x9315us-2.7* x9315u f 0 to 70 8 ld soic x9315usz-2.7* (note) x9315u z f 0 to 70 8 ld soic (pb-free) x9315usi-2.7* x9315u g -40 to 85 8 ld soic x9315usiz-2.7* (note) x9315u z g -40 to 85 8 ld soic (pb-free) x9315tm-2.7* aei 100 0 to 70 8 ld msop x9315tmz-2.7* (note) ddp 0 to 70 8 ld msop (pb-free) x9315tmi-2.7* ady -40 to 85 8 ld msop x9315tmiz-2.7* (note) ddm -40 to 85 8 ld msop (pb-free) x9315ts-2.7* x9315t f 0 to 70 8 ld soic x9315tsz-2.7* (note) x9315t z f 0 to 70 8 ld soic (pb-free) x9315tsi-2.7* x9315t g -40 to 85 8 ld soic x9315tsiz-2.7* (note) x9315t z g -40 to 85 8 ld soic (pb-free) note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. *add "t1" suffix for tape and reel. ordering information (continued) part number part marking v cc limits (v) r total (k ? ) temp range (c) package x9315
4 fn8179.1 september 15, 2005 pin descriptions r h /v h and r l /v l the high (r h /v h ) and low (r l /v l ) terminals of the x9315 are equivalent to the fixed terminals of a mechanical potentiometer. the minimum voltage is v ss and the maximum is v cc . the terminology of r l /v l and r h /v h references the relative position of the terminal in relation to wiper movement direction selected by the u/d input, and not the voltage potential on the terminal. r w /v w r w /v w is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the control inputs. the wiper terminal series resistance is typically 200 ? at v cc = 5v. up/down (u/d ) the u/d input controls the direction of the wiper movement and whether the counter is incremented or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the u/d input. chip select (cs ) the device is selected when the cs input is low. the current counter value is stored in nonvolatile memory when cs is returned high while the inc input is also high. after the store operation is complete the x9315 will be placed in the low power standby mode until the device is selected once again. pin configuration principles of operation there are three sections of the x9315: the input control, counter and decode section; the nonvolatile memory; and the resistor array. the input cont rol section operates just like an up/down counter. the output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. under the proper conditions the contents of t he counter can be stored in nonvolatile memory and retained for future use. the resistor array is comprised of 31 individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that tr ansfers the connection at that point to the wiper. the wiper, when at either fi xed terminal, acts like its mechanical equivalent and does not move beyond the last position. that is, the counter does not wrap around when clocked to either extreme. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. if the wiper is moved several positions, multiple taps are connected to the wiper for t iw (inc to v w change). the r total value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. when the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low the device is selected and enabled to respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depending on the state of the u/d input) a five bit counter. the output of this counter is decoded to select one of thirty two wiper positions along the resistive array. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. the system may select the x9315, move the wiper and deselect the device without havi ng to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as described above and once the new position is reached, the system must keep inc low while taking cs high. the new wiper position will be maintained until pin names symbol description r h /v h high terminal r w /v w wiper terminal r l /v l low terminal v ss ground v cc supply voltage u/d up/down control input v cc cs inc u/d r h /v h v ss 1 2 3 4 8 7 6 5 x9315 dip/soic/msop r l /v l r w /v w inc increment control input cs chip select control input pin names symbol description x9315
5 fn8179.1 september 15, 2005 changed by the system or until a power-up/down cycle recalled the previously stored data. this procedure allo ws the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. the adjustments might be based on user preference, system parameter changes due to temperature drift, etc... the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. symbol table mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position h x x standby current l x no store, return to standby waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x9315
6 fn8179.1 september 15, 2005 notes: (1) absolute linearity is utilized to determi ne actual wiper voltage versus expected voltage = (v w(n) (actual) - v w(n) (expected)) = 1 ml maximum. (2) relative linearity is a measure of the error in step size between taps = r w(n+1) - [r w(n) + ml] = 0.2 ml. (3) 1 ml = minimum increment = r tot /31. (4) typical values are for t a = 25c and nominal supply voltage. (5) this parameter is periodically sampled and not 100% tested absolute maximum ratings recommended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on cs , inc , u/d , v h , v l and v cc with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v ? v = |v h ?v l | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300c i w (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5ma temperature (commercial) . . . . . . . . . . . . . . . . . . . . . 0c to +70c temperature (industrial). . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (v cc ) (note 4) limits x9315. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% x9315-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. potentiometer ch aracteristics (over recommended operating conditions unless otherwise stated.) symbol parameter test conditions/notes limits min typ max. unit end to end resistance tolerance 20 % v vh v h terminal voltage 0 v cc v v vl v l terminal voltage 0 v cc v power rating r total 10k ? 10 mw r w wiper resistance i w = 1ma, v cc = 5v 200 400 ? r w wiper resistance i w = 1ma, v cc = 2.7v 400 1000 ? i w wiper current 3.75 ma noise ref: 1khz -120 dbv resolution 3% absolute linearity (1) v w(n)(actual) - v w(n)(expected) 1 mi (3) relative linearity (2) v w(n + 1) - [v w(n) + mi ]0.2mi (3) r total temperature coefficient 300 ppm/c ratiometric temperature coefficient 20 ppm/c c h /c l /c w potentiometer capacitances see circuit #3 10/10/25 pf dc electrical specifications (over recommended operating conditi ons unless otherwise specified. symbol parameter test conditions limits unit min typ (4) max i cc1 v cc active current (increment) cs = v il , u/d = v il or v ih and inc = 0.4v @ max. t cyc 50 a i cc2 v cc active current (store) (eeprom store) cs = v ih , u/d = v il or v ih and inc = v ih @ max. t wr 400 a i sb standby supply current cs = v cc - 0.3v, u/d and inc = v ss or v cc - 0.3v 1a i li cs , inc , u/d input leakage current v in = v ss to v cc 10 a v ih cs , inc , u/d input high voltage v cc x 0.7 v cc + 0.5 v v il cs , inc , u/d input low voltage -0.5 v cc x 0.1 v c in (5) cs , inc , u/d input capacitance v cc = 5v, v in = v ss , t a = 25c, f = 1mhz 10 pf x9315
7 fn8179.1 september 15, 2005 endurance and data retention parameter min unit minimum endurance 100,000 data changes per bit data retention 100 years test circuit #1 test circuit #2 circuit #3 spice macro model test point v w /r w v h /r h v l /r l v s force current v l vw test point v h /r h v w /r w v l /r l c h c l r w 10pf 10pf r h r l r total c w 25pf ac conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input reference levels 1.5v ac electrical specifications (over recommended operating conditi ons unless otherwise specified) symbol parameter limits unit min typ (6) max t cl cs to inc setup 100 ns t ld inc high to u/d change 100 ns t di u/d to inc setup 2.9 s t ll inc low period 1 s t lh inc high period 1 s t lc inc inactive to cs inactive 1 s t cph cs deselect time (no store) 100 ns t cph cs deselect time (store) 10 ms t iw inc to vw change 1 5 s t cyc inc cycle time 4 s t r , t f (7) inc input rise and fall time 500 s t pu (7) power-up to wiper stable 5s t r v cc (7) v cc power-up rate 0.2 50 v/ms t wr store cycle 510ms x9315
8 fn8179.1 september 15, 2005 power-up and down requirements there are no restrictions on the power-up or power-down conditions of v cc and the voltages applied to the potentiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc ramp rate spec is always in effect. ac timing notes: (6) typical values are for t a = 25c and nominal supply voltage. (7) this parameter is not 100% tested. (8) mi in the a.c. timing diagram refers to the minimum incremental change in the v w output due to a change in the wiper position. performance characteristics (typical) typical noise cs inc u/d v w t ci t il t ih t cyc t id di t iw mi (8) t ic t cph t f t r 10% 90% 90% (store) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 102030405060708090100 frequency (khz) noise (db) 110 120 130 140 150 160 170 180 190 200 x9315
9 fn8179.1 september 15, 2005 typical rtotal vs. temperature typical total resistance temperature coefficient typical wiper resistance 10000 9800 9600 9400 9200 9000 8800 8600 8400 8200 8000 rtotal -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 temperature 85 95 105 115 125 c -55 -350 -300 -250 -200 -150 -100 -50 0 -45 -35 -25 -15 -5 5 15 25 35 temperature ppm 45 55 65 75 85 95 105 115 125 c 0 0 100 200 300 400 rw ( ?) 500 600 700 800 2 4 6 8 10 12 14 16 tap 18 20 22 24 26 28 30 32 v cc = 2.7v x9315
10 fn8179.1 september 15, 2005 typical absolute% error per tap position typical relative% error per tap position applications information electronic digitally controlled (xdcp) potentiometers provide three powerful application advan tages; (1) the variability and reliability of a solid-state potent iometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. 40.0% 30.0% 20.0% 10.0% 0.0% -10.0% -20.0% -30.0% -40.0% 0 3 6 9 12 15 tap absolute% error 18 21 24 27 30 20.0% 15.0% 10.0% 5.0% 0.0% -5.0% -10.0% -15.0% -20.0% 03691215 relative% error 18 21 24 27 30 tap x9315
11 fn8179.1 september 15, 2005 basic configurations of electronic potentiometers basic circuits v r v w /r w v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current v h v l cascading techniques buffered reference voltage ? + +5v r 1 +v -5v v w v ref v out op-07 r w /v w r w /v w +v +v +v x (a) (b) v out = v w /r w noninverting amplifier + ? v s v o r 2 r 1 v o = (1 + r 2 /r 1 )v s lm308a voltage regulator r 1 r 2 i adj v o (reg) = 1.25v (1 + r 2 /r 1 ) + i adj r 2 v o (reg) v in 317 comparator with hysteresis v ul = {r 1 /(r 1 + r 2 )} v o (max) v ll = {r 1 /(r 1 + r 2 )} v o (min) + ? v s v o r 2 r 1 } } lt311a +5v -5v (for additional circuits see an115) x9315
12 fn8179.1 september 15, 2005 packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ. r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ. 8-lead miniature small outlin e gull wing package type m note: 1. all dimensions in inches and (millimeters) 0.220" 0.0256" typical 0.025" typical 0.020" typical 8 places footprint ref. x9315
13 fn8179.1 september 15, 2005 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62) plane x9315
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8179.1 september 15, 2005 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint x9315
x9315 printer friendly version digitally controlled potentiometer (xdcp?) datasheets, related docs & simulations description key features parametric data application diagrams related devices ordering information part no. design-in status temp. package msl price us $ x9315tm active comm 8 ld msop 1 1.52 x9315tm-2.7 active comm 8 ld msop 1 1.67 x9315tm-2.7t1 active comm 8 ld msop t+r 1 1.67 x9315tmi active ind 8 ld msop 1 1.75 x9315tmi-2.7 active ind 8 ld msop 1 1.92 x9315tmi-2.7c7898 active ind 8 ld msop t+r 1 x9315tmi-2.7t1 active ind 8 ld msop t+r 1 1.92 x9315tmi-2.7t2 active ind 8 ld msop t+r 3 1.92 x9315tmit1 active ind 8 ld msop t+r 1 1.75 x9315tmiz active ind 8 ld msop 2 1.75 x9315tmiz-2.7 active ind 8 ld msop 2 1.92 x9315tmiz-2.7t1 active ind 8 ld msop t+r 2 1.92 x9315tmizt1 active ind 8 ld msop t+r 2 1.75 x9315tmt1 active comm 8 ld msop t+r 1 1.52 x9315tmz active comm 8 ld msop 2 1.52 x9315tmz-2.7 active comm 8 ld msop 2 1.67 x9315tmz-2.7t1 active comm 8 ld msop t+r 2 1.67 x9315tmzt1 active comm 8 ld msop t+r 2 1.52 x9315tp active comm 8 ld pdip n/a 1.45 x9315tp-2.7 active comm 8 ld pdip n/a 1.59 x9315tpi active ind 8 ld pdip n/a 1.66 x9315tpi-2.7 active ind 8 ld pdip n/a 1.83 x9315ts active comm 8 ld soic 1 1.30 x9315ts-2.7 active comm 8 ld soic 1 1.59 x9315ts-2.7t1 active comm 8 ld soic t+r 1 1.59 x9315tsi active ind 8 ld soic 1 1.62 x9315tsi-2.7 active ind 8 ld soic 1 1.83 x9315tsi-2.7c7898 active ind 8 ld soic 1
x9315tsi-2.7t1 active ind 8 ld soic t+r 1 1.83 x9315tsit1 active ind 8 ld soic t+r 1 1.62 x9315tsiz active ind 8 ld soic 1 1.62 x9315tsiz-2.7 active ind 8 ld soic 1 1.83 x9315tsiz-2.7t1 active ind 8 ld soic t+r 1 1.83 x9315tsizt1 active ind 8 ld soic t+r 1 1.62 x9315tst1 active comm 8 ld soic t+r 1 1.30 x9315tsz active comm 8 ld soic 1 1.30 x9315tsz-2.7 active comm 8 ld soic 1 1.59 x9315tsz-2.7t1 active comm 8 ld soic t+r 1 1.59 x9315tszt1 active comm 8 ld soic t+r 1 1.30 x9315um active comm 8 ld msop 1 1.52 x9315um-2.7 active comm 8 ld msop 1 1.67 x9315um-2.7c7958 active comm 8 ld msop t+r 1 x9315um-2.7c7964 active comm 8 ld msop t+r 1 x9315um-2.7t1 active comm 8 ld msop t+r 1 1.67 x9315um-2.7t1c7958 active comm 8 ld msop t+r 1 x9315um-2.7t1c7964 active comm 8 ld msop t+r 1 x9315um-2.7t2 active comm 8 ld msop t+r 3 1.67 x9315um-2.7t2c7964 active comm 8 ld msop t+r 3 x9315umi active ind 8 ld msop 1 1.75 x9315umi-2.7 active ind 8 ld msop 1 1.92 x9315umi-2.7c7898 active ind 8 ld msop 1 x9315umi-2.7c7984 active ind 8 ld msop 1 x9315umi-2.7t1 active ind 8 ld msop 1 1.92 x9315umi-2.7t1c7898 active ind 8 ld msop t+r 1 x9315umi-2.7t1c7975 active ind 8 ld msop t+r 1 x9315umi-2.7t1c7984 active ind 8 ld msop t+r 1 x9315umi-2.7t2 active ind 8 ld msop t+r 3 1.92 x9315umi-2.7t2c7898 active ind 8 ld msop t+r 3 x9315umic7898 active ind 8 ld msop t+r 1 x9315umit1 active ind 8 ld msop t+r 1 1.75 x9315umit2 active ind 8 ld msop t+r 3 1.75 x9315umit2c7898 active ind 8 ld msop t+r 3 x9315umiz active ind 8 ld msop 2 1.75
x9315umiz-2.7 active ind 8 ld msop 2 1.92 x9315umiz-2.7t1 active ind 8 ld msop t+r 2 1.92 x9315umizt1 active ind 8 ld msop t+r 2 1.75 x9315umt1 active ind 8 ld msop t+r 1 1.52 x9315umz active comm 8 ld msop 2 1.52 x9315umz-2.7 active ind 8 ld msop 2 1.67 x9315umz-2.7c7964 active comm 8 ld msop 2 x9315umz-2.7t1 active comm 8 ld msop 2 1.67 x9315umz-2.7t1c7964 active comm 8 ld msop 2 x9315umzt1 active comm 8 ld msop t+r 2 1.52 x9315up active comm 8 ld pdip n/a 1.45 x9315up-2.7 active comm 8 ld pdip n/a 1.59 x9315upi active ind 8 ld pdip n/a 1.66 x9315upi-2.7 active ind 8 ld pdip n/a 1.83 x9315upic7898 active ind 8 ld pdip n/a x9315us active comm 8 ld soic 1 1.30 x9315us-2.7 active comm 8 ld soic 1 1.59 x9315us-2.7t1 active comm 8 ld soic t+r 1 1.59 x9315us-2.7t2 active comm 8 ld soic t+r 3 1.59 x9315usi active ind 8 ld soic 1 1.62 x9315usi-2.7 active ind 8 ld soic 1 1.83 x9315usi-2.7c7898 active ind 8 ld soic t+r 1 x9315usi-2.7t1 active ind 8 ld soic t+r 1 1.83 x9315usit1 active ind 8 ld soic t+r 1 1.62 x9315usiz active ind 8 ld soic 1 1.62 x9315usiz-2.7 active ind 8 ld soic 1 1.83 x9315usiz-2.7t1 active ind 8 ld soic t+r 1 1.83 x9315usizt1 active ind 8 ld soic t+r 1 1.62 x9315ust1 active ind 8 ld soic t+r 1 1.30 x9315ust2 active ind 8 ld soic t+r 3 1.30 x9315usz active comm 8 ld soic 1 1.30 x9315usz-2.7 active comm 8 ld soic 1 1.59 x9315usz-2.7t1 active comm 8 ld soic t+r 1 1.59 x9315uszt1 active comm 8 ld soic t+r 1 1.30 x9315wm active comm 8 ld msop 1 1.92 x9315wm-2.7 active comm 8 ld msop 1 1.68 x9315wm-2.7c7975 active comm 8 ld msop 1 x9315wm-2.7t1 active comm 8 ld msop t+r 1 1.68 x9315wm-2.7t1c7964 active comm 8 ld msop t+r 1
x9315wm-2.7t2 active comm 8 ld msop t+r 3 1.68 x9315wmi active ind 8 ld msop 1 1.92 x9315wmi-2.7 active ind 8 ld msop 1 2.12 x9315wmi-2.7c7898 active ind 8 ld msop 1 x9315wmi-2.7c7941 active ind 8 ld msop 1 x9315wmi-2.7t1 active ind 8 ld msop t+r 1 2.12 x9315wmi-2.7t1c7898 active ind 8 ld msop 1 x9315wmi-2.7t2 active ind 8 ld msop t+r 3 2.12 x9315wmi-2.7t2c7898 active ind 8 ld msop 3 x9315wmi-2.7t2c7941 active ind 8 ld msop 3 x9315wmit1 active ind 8 ld msop t+r 1 1.92 x9315wmit2 active ind 8 ld msop t+r 3 1.92 x9315wmiz active ind 8 ld msop 2 1.92 x9315wmiz-2.7 active ind 8 ld msop 2 2.12 x9315wmiz-2.7t1 active ind 8 ld msop t+r 2 2.12 x9315wmizt1 active ind 8 ld msop t+r 2 1.92 x9315wmt1 active comm 8 ld msop t+r 1 1.92 x9315wmt1c7517 active comm 8 ld msop 1 x9315wmz active comm 8 ld msop 2 1.92 x9315wmz-2.7 active comm 8 ld msop 2 1.68 x9315wmz-2.7t1 active comm 8 ld msop t+r 2 1.68 x9315wmzt1 active comm 8 ld msop t+r 2 1.92 x9315wp active comm 8 ld soic n/a 1.30 x9315wp-2.7 active comm 8 ld soic n/a 1.44 x9315wpc7898 active comm 8 ld soic n/a x9315wpi active ind 8 ld soic n/a 1.62 x9315wpi-2.7 active ind 8 ld soic n/a 1.79 x9315wpi-2.7c7898 active ind 8 ld soic n/a x9315ws active comm 8 ld soic 1 1.30 x9315ws-2.7 active comm 8 ld soic 1 1.44 x9315ws-2.7c7898 active comm 8 ld soic 1 x9315ws-2.7t1 active comm 8 ld soic t+r 1 1.44 x9315ws-2.7t2 active comm 8 ld soic t+r 3 1.44 x9315wsc7898 active comm 8 ld soic 1 x9315wsi active ind 8 ld soic 1 1.62 x9315wsi-2.7 active ind 8 ld soic 1 1.79 x9315wsi-2.7c7898 active ind 8 ld soic 1 x9315wsi-2.7t1 active ind 8 ld soic t+r 1 1.79 x9315wsi-2.7t1c7898 active ind 8 ld soic 1 x9315wsi-2.7t2c7898 active ind 8 ld soic 3
x9315wsic7898 active ind 8 ld soic 1 x9315wsic7942 active ind 8 ld soic 1 x9315wsit1 active ind 8 ld soic t+r 1 1.62 x9315wsit1c7898 active ind 8 ld soic 1 x9315wsit1c7942 active ind 8 ld soic 1 x9315wsit2 active ind 8 ld soic t+r 3 1.62 x9315wsit2c7898 active ind 8 ld soic 3 x9315wsiz active ind 8 ld soic 1 1.62 x9315wsiz-2.7 active ind 8 ld soic 1 1.79 x9315wsiz-2.7t1 active ind 8 ld soic t+r 1 1.79 x9315wsizt1 active ind 8 ld soic t+r 1 1.62 x9315wst1 active comm 8 ld soic t+r 1 1.30 x9315wst1c7975 active comm 8 ld soic 1 x9315wst2 active comm 8 ld soic t+r 3 1.30 x9315wsz active comm 8 ld soic 1 1.30 x9315wsz-2.7 active comm 8 ld soic 1 1.44 x9315wsz-2.7t1 active comm 8 ld soic t+r 1 1.44 x9315wszt1 active comm 8 ld soic t+r 1 1.30 xlabview01 active n/a 91.77 xlabview01z active eval board n/a 91.77 x9315tmiz-2.7t2 coming soon ind 8 ld msop t+r 3 x9315usz-2.7t2 coming soon comm 8 ld soic t+r 3 x9315wmiz-2.7t2 coming soon ind 8 ld msop t+r 3 x9315wmz-2.7t2 coming soon comm 8 ld msop t+r 3 1.68 x9315wsizt2 coming soon comm 8 ld soic t+r 3 x9315umiz-2.7t2 inactive ind 8 ld msop t+r 3 x9315umizt2 inactive ind 8 ld msop t+r 3 x9315umz-2.7t2 inactive comm 8 ld msop t+r 3 1.67 x9315uszt2 inactive comm 8 ld soic t+r 3 x9315wmizt2 inactive ind 8 ld msop t+r 3 x9315wsz-2.7t2 inactive comm 8 ld soic t+r 3 1.44 x9315wszt2 inactive comm 8 ld soic t+r 3 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the intersil x9315 is a digitally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a 3-wire interface.
the potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the cs , u/ d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: $$ control $$ parameter adjustments $$ signal processing key f eatures solid-state potentiometer 3-wire serial interface 32 wiper tap points wiper position stored in nonvolatile memory and recalled on power-up 31 resistive elements temperature compensated end to end resistance range 20% terminal voltage, 0 to v cc low power cmos v cc = 2.7v or 5v active current, 50/400a max. standby current, 1a max. high reliability endurance, 100,000 data changes per bit register data retention, 100 years r total values = 10k , 50k , 100k packages 8 ld soic, msop and pdip pb-free plus anneal available (rohs compliant) related documentation application note(s): a compendium of application circuits for intersil?s digitally-controlled (xdcp) potentiometers a primer on digitally-controlled potentiometers application of intersil digitally controlled potentiometers (xdcp?) as hybrid analog/digital feedback system control elements dc/dc module trim with digital potentiometers designing power supplies using intersil?s xdcp mixed signal products power supply and dc to dc converter control using intersil digitally controlled potentiontiometers (xdcps) putting analog on the bus shaft encoder drives multiple intersil digitally controlled potentiontiometers (xdcps) third generation e 2 pot devices from intersil-part 1 tone, balance, and volume control using a quad xdcp working with the intersil 3-wire dcp devices datasheet(s): digitally controlled potentiometer (xdcp?) technical brief(s): converting a fixed pwm to an adjustable pwm evaluation board(s): intersil_xdcp_test_utility_manual_rev_3.2.3.pdf labview_xdcp_software.zip labview_xdcp_upgrade_3.2.3.zip readme_xicorlabview_v3.2.3.txt xdcp_vref evaluation board kit documentation and software accesshw.zip technical homepage: digitally controlled potentiometers (dcps) and capacitors (dccs) precision analog homepage
parametric data number of dcps single number of taps 32 memory type non-volatile bus interface type 3-wire (up/down) resistance options (k ) 10, 50, 100 v cc range (v) 2.7 to 5.5 dcp differential terminal voltage (v) 0 to +5.5 terminal voltage range v l to v h (v) 0 to v cc resistance taper linear wiper current (ma) 1 wiper resistance ( ) 200 standby current i sb ( a) 1 application block diagrams digital projector related devices parametric table x9313 digitally controlled potentiometer (xdcp?), linear, 32 taps, 3 wire interface, terminal voltages v cc x9314 single digitally controlled potentiometer (xdcp?) x93154 digitally controlled potentiometer (xdcp?) x93155 digitally controlled potentiometer (xdcp?) x93156 single digitally controlled potentiometer (xdcp?), low noise, low power, 3 wire up/down, 32 taps x9511 single digitally-controlled (xdcp?) potentiometer (push button controlled) about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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